A designer of computer chips has to think about a lot of things, such as clock trees.
“Whenever you put in the clock tree, it is a very difficult step,” Kam Kittrell, the senior product management group director at Cadence Design Systems, one of the chief tool builders for chip designers, told ZDNet in an interview via Zoom.
The subject of the discussion was what Cadence calls its Cerebrus Intelligent Chip Explorer, a newly released software program meant to assist chip designers by using machine learning to automate some of the steps involved.
Cerebrus is part of the tool chain, as it’s called, that Cadence sells that goes from a very high-level language “down to the last via and wire,” as Kittrell puts, the individual parts of a chip. It is like a car assembly line of hundreds of steps, as he notes, and Cerebrus inserts a new segment into that assembly line that takes over some of the hand work of a designer and automates it with machine learning routines.
Cadence claims Cerebrus can increase human chip designers’ productivity by an order of magnitude while also boosting the three main metrics of chip quality — performance, power efficiency, and how compact the square area is — by as much as 20%. Those three metrics are typically referred to as “PPA,” power, performance, area.
Cerebrus runs on AWS and other cloud platforms but can also be run on-premise.
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The impetus for the tool is the fact that chip complexity is being accelerated at the same time chip manufacturing is up against ever more challenging physical constraints in the breakdown of Moore’s Law close to the atomic scale.
“A few years ago, it was cell phones driving chip design, and then cloud came along, and then there’s 5G on top of it, and AI,” is how Kitrell summarized the march of technologies needing to be integrated on chip. “And auto makers are saying they need 5G and AI together, and the chips are just getting harder and harder to design.”
With the shrink of transistors to dimensions of three billionths of a meter in the parts being designed by Apple and Intel and others, and the packing together of multiple billions of those transistors in an area measuring perhaps only a couple square millimeters, satisfying all those AI and 5G capabilities in a single part according to PPA requirements is daunting.
“We’ve got multiple vectors coming together, and it gets harder and harder as we go into deeper technology nodes,” said Kittrell.
The secret to why Cerebrus works is that the tool chain is already “very algorithmic,” said Kittrell. Engineers are already in the habit of multi-variate calculations to arrive at optimal solutions. “These are really tough math-intense problems to solve.”
To try different solutions to those problems, programmers run experiments.
“You take a billion instances of a netlist,” the machine’s descriptions of the parts that fit together to make a circuit, “and they’re all connected together,” and the optimization problem is one of “where you place them in order to reduce the connectivity distance, how you connect them with five layers of metal,” he said.
The best programmers can run three to five experiments at any moment in time, said Kittrell. Cerebras can run 50 to 100 simultaneously.
“You give it a vector, what do you care about,” from among the PPA, explained Kitrell. Cerebrus “can find a good path to a solution quickly.” An engineer can hold one variable constant, such as chip area, and have Cerebrus experiment with the other metrics. At the end of experiments, Cerebrus will replay experiments to show each step in the optimization, and an engineer can use any point along that chain of steps as a new starting point for a new optimization.
The optimizations can also be saved, so that a customer can amass a library of optimizations that then become a basis for future work.
Cadence customers, such as Renesas of Japan, which makes industrial and automotive chips, as well as the contract chip-making division of Samsung, say that Cerebrus has helped improve the PPA of their chips, and engineers’ productivity.
The guts to making Cerebrus are what’s known as reinforcement learning. However, Kitrell declined to specify details of the RL approach. “We are not revealing a lot of detail other than that it is ML with reinforcement learning capabilities,” he said, noting that the field of AI in chip design is “a highly competitive area right now.”
Cadence obviously has amassed a wealth of specific knowledge about the process of chip design, and that can serve to inform the RL.
Which brings us to clock trees.
In case you didn’t know it, clock trees are a way that the fundamental drum beat of a computer chip, the oscillating clock signal that maintains the cadence of operations, is distributed throughout the chip’s circuits.
The problem is that making a good clock tree is not something that can be done in isolation. Ideally it can be done in combination with numerous other variables, in a kind of holistic way, to solve the PPA problem. “It’s very difficult to get a good clock tree in, but you don’t just want the best result in the end,” Kitrell explained.
With help from Cerebrus’s RL, the clock frequency can become just one variable packaged into making the best chip possible.
The RL models that Cerebrus uses are not usually trained in a particular way in advance, because “anything I pre-trained may be like a crystal vase, put one chip in it and the whole thing is ruined,” given the vast number of variables, explained Kitrell. “So the requirement is that even without training we should be able to find solutions fast.”
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At the same time, the results of previous experiments can be adapted to a new set of variables.
Asked about how much of Cerebrus was designed in-house, Kitrell observed, “of course we are standing on the shoulders of of a lot of good tech,” explaining that the wealth of readily available open-source software on which to build means “we would not have come up with this five or six years ago.” At the same time, Cadence is filing patents on the Cerebrus program and investing in its continued development.
Asked whether the program will replace human invention, Kitrell said there is still room for imagining possibilities that don’t even exist.
You may have heard of Google’s recent work using deep learning to solve the problem of coming up with a good floor plan for circuit layout. Kitrell, who knows the authors of the work, considers the Google work as an “inspiration,” but predicts it won’t replace human engineers using tools.
“The demand for engineers right now is through the roof,” said Kitrell, “and we will make it possible for people to get work done with the engineers they have now, rather than putting anyone on the bread line.
He added, “We’d be happy to benchmark against the guys at Google.”
